Modelsim user's manual - detecting infinite zero-delay loops

Limited class logging and viewing has been added to this release as a beta feature. Declarations in initialization of for loop is also supported. If a large number of delta cycles occur without advancing time, it is usually a symptom of an infinite zero delay loop in the design. In order to detect the presence of these loops, modelsim defines a limit, the iteration limit, on the number of successive deltas that can occur. The problem occurs with two blocks that have some dependencies between them. When a key is pressed, a sequence of bytes is sent serially over the twowire bus. Two common causes are a loop that has no exit, or a series of gates with zero delays where the outputs are connected back to the inputs. I am using the runtime setup of the simulator to get around this potential. Mentor graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice, and the reader should, in all cases, consult mentor graphics to determine whether any changes have been made. Jaime andres aranguren cardona wrote in message news. In order to detect when keys are initially pressed and then released, the keyboard will send a sequence of bytes for each key press.

A zerodelay force command causes the change to occur in the current rather than the next simulation delta cycle. After retriggering a certain process several hundreds of time without seeing simulation time 0 ns advance modelsim will abort and show this indefinite loop. Unauthorized copying, duplication, or other reproduction is prohibited without the written consent of model technology. Zero delay loop in verilog design verification academy. Possible zero delay oscillation detected where simulation time can not advance.

Detecting infinite zerodelay loops if a large number of deltas occur without advancing time, it is usually a symptom of an infinite zerodelay loop in the design. The modelsim reference manual lists all of the exit codes quote start 211 segmentation violation sigsegv quote end basically, modelsim has crashed. It is probably something in your code causing the crash when it shouldnt. In order to detect the presence of these loops, modelsim defines a. To fix this, whether add a wait statement, or use sensitivity list.

Ive read that that means theres some process loop the simulator is stuck in, but how can i find out which one is the cause and how to fix it. Check the user manual section detecting infinite zerodelay loops. Both compiles were successful but the test bench had a few warnings. You can avoid this by inserting a wait statement for the signals that you want to keep track of, by adding the sensitivity list which does basically the same since a sensitivity list. Also, a process is reexecuted as soon as it finishes. No one is permitted to use these marks without the prior written.

If this screen is not available, you can display it by selecting help welcome. It is divided into fourtopics, which you will learn more about in subsequent. Refer to user s manual for a more detailed description. The warnings are due to the way i designed the test bench in that it is effectively an infinite loop. File and directory pathnames several modelsim commands have arguments that point to files or directories. For based numbers in vhdl, modelsim tran slates each 1 or 0 to the appropriate value for the numbers. Due to race condition or ambiguous coding style zero delay loop may get generated which results in simulation hung or infinite simulation time. For the windows platform, you must install the compilers manually. Verilogger simplifying the design of digital systems. Modelsim tutorial jee2600 page 12 both files were compiled since the compile all option was selected.

A pll is a feedback control system that automatically adjusts the phase of a locally generated signal to match the phase of an input signal. You will need to look in the questa user manual or search the internet for detecting infinite zerodelay loops dave rich, verification architect, siemens eda siemens digital industries software. I tried stepping through the code but after 10 minutes of clicking step ise crashed. Simulation can be resumed from the command prompt using any of the normala runa commands.

If you are simulating gates especially on very large designs just increase the interation limit on modelsim. Im kind of puzzled why this is happening, and where to look for. Each key on the keyboard is given a unique scancode see nexys2 board user manual. Any chance you can post all the code here so we can try.

This lesson provides a brief conceptual overview of the modelsim simulation environment. Thanks mike, running the sim twice as you suggested might be my answer, it doesnt take long. Library provides an environment for you to compile and simulate your. Support for modelsim is available from your fpga vendor. However it isnt clear how to troubleshoot the foreign parts of your elaborated design model. This is taken care of by a 30second timeout and a certain memory limit. Another frequent possibility is that the infinite loop allocates memory, in which case it quickly exhausts all available memory.

Modelsim users manual detecting infi nite zerodelay loops you could troubleshoot. In vhdl, a processs execution time is instantaneous. Note that the iteration limit can be changed using switch maxdeltaid. In my course on algorithms and data structures, our autograder has to deal with student submissions that sometimes get into infinite loops.

Aug 20, 2001 modelsim vhdl, modelsim vlog, modelsim lnl, and modelsim plus are produced by model technology incorporated. Mentor graphics reserves the right to make changes in specifications and other information contai ned in this publication without prior notice, and the. Youll quickly find out where your infinite loop is. Feedback loops may cause endless oscillation user or the engine must take action to interrupt uncontrolled oscillation usually bad hdl design, e. Some examples obtained from mentor modelsim manual. This document is for information and instruction purposes. Refer to systemc simulation in the users manual for more details. I have a problem with simvision hanging in an endless loop. There might be zerodelay loops that exist in your design. If the modelsim software you are using is a later release, check the readme file that accompanied the software. As for running quartus first, im relying on it to give me gate level timings and pass that along to modelsim. Enhanced for loop is implemented as described in 8. For more information about using project files, see the modelsim users manual. It supports multiple initialization and multiple step assignments.

When the delta limit is hit, the simulator will interrupt the simulation and place the user at the simulators interactive command prompt so that the source of the infinite loop can be analyzed and debugged. Modelsim users manual detecting infi nite zerodelay loops hans. Try inserting assert statements in the testbench to print out the progress of your simulation. And these options are very useful to figure out that which file is troubling for zero delay infinite loop from my simulation log. If a large number of delta cycles occur without advancing time, it is usually a symptom of an infinite zerodelay loop in the design. Check the user manual section detecting infinite zero delay loops. The information in this manual is subject to change without notice and does not. Before jumping into using modelsim, there are two important components you should get familiar with. Problem with simvision hanging in an endless loop logic.